Double Data Rate (DDR) signals may be received onto an integrated circuit via integrated circuit terminals. In the case of the Interlaken signaling protocol, these DDR signals may include a DDR data signal, a DDR sync signal, and an associated DDR clock signal. Within the integrated circuit, a subcircuit is to receive and use these DDR signals. The subcircuit is, however, located a substantial distance away from the terminals and there are substantial signal propagation delays between the terminals and corresponding inputs to the subcircuit. If the DDR signals are to pass across this substantial distance from the terminals to the subcircuit inputs, then it may be difficult or cumbersome to maintain the necessary timing relationships between the DDR data, DDR sync and DDR clock signals such that the subcircuit will properly receive the DDR data without incurring setup time and/or hold time violations. To prevent such setup and/or hold time violations, the data, sync and clock signal conductors between the integrated circuit terminals and the subcircuit must generally be carefully laid out to have adequately matched propagation delays.